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| (R) HI-303/883 Data Sheet November 2003 FN6058 Dual SPDT CMOS Analog Switch The HI-303/883 switch is a monolithic device fabricated using CMOS technology and the Intersil Dielectric Isolation process. This switch features break-before-make switching, low and nearly constant ON resistance over the full analog signal range, and low power dissipation. The HI-303/883 is TTL compatible and has a logic "0" condition with an input less than 0.8V and a logic "1" condition with an input greater than 4.0V. The HI-303/883 is pin-for-pin compatible with the industry standard Siliconix DG303. The device is available in a 14 pin Ceramic DIP. The HI-303/883 operates over the -55C to +125C temperature range. Features * This Circuit is Processed in Accordance to MIL-STD-883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. * Analog Signal Range (15V Supplies). . . . . . . . . . . .15V * Low Leakage (+25C) . . . . . . . . . . . . . . . . . . . .1nA (Max) * Low Leakage (+125C) . . . . . . . . . . . . . . . . .100nA (Max) * Low ON Resistance . . . . . . . . . . . . . . . . . . . . . 50 (Max) * Charge Injection . . . . . . . . . . . . . . . . . . . . . . . . 30pC (Typ) * TTL Compatible * System Switch Elements * Low Operating Power Pinout HI1-303/883 (CERAMIC DIP) TOP VIEW * Compatible with DG303 Applications * Sample and Hold, i.e. Low Leakage Switching * Op Amp Gain Switching, i.e. Low ON Resistance * Portable, Battery Operated Circuits * Low Level Switching Circuits * Dual or Single Supply Systems NC S3 D3 D1 S1 A1 GND 1 2 3 4 5 6 7 14 V+ 13 S4 12 D4 11 D2 10 S2 9 A2 8 V- LOGIC 0 1 SW1 SW2 Off On SW3 SW4 On Off 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2003. All Rights Reserved All other trademarks mentioned are the property of their respective owners. HI-303/883 Absolute Maximum Ratings Voltage Between V+ and V- Terminals. . . . . . . . . . . . . . . . . . . . .44V VSUPPLY to Ground (V+, V-) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22V Analog Input Voltage, (+VS ). . . . . . . . . . . . . . . . . . +VSUPPLY +1.5V Analog Input Voltage, (-VS ) . . . . . . . . . . . . . . . . . . . -VSUPPLY -1.5V Digital Input Voltage, (+VA) . . . . . . . . . . . . . . . . . . . .+VSUPPLY +4V Digital Input Voltage, (-VA) . . . . . . . . . . . . . . . . . . . . . .-VSUPPLY -4V Peak Current (S or D) (Pulse at 1ms, 10% Duty Cycle Max). . . . . . . . . . . . . . . . . . 40mA Continuous Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30mA Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175C Storage Temperature Range . . . . . . . . . . . . . . . . . .-65C to +150C Lead Temperature (Soldering 10 sec) . . . . . . . . . . . . . . . . . . . 275C Thermal Information Thermal Resistance JA (oC/W) JC (oC/W) CERDIP Package. . . . . . . . . . . . . . . . . 88 24 Package Power Dissipation at 75oC Ceramic DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . 0.85W/oC Package Power Dissipation Derating Factor above +75oC Ceramic DIP Package . . . . . . . . . . . . . . . . . . . . . . . 11.36mW/oC Recommended Operating Conditions Operating Temperature Range . . . . . . . . . . . . . . . -55oC to +125oC Operating Supply Voltage Range (VSUPPLY) . . . . . . . . . . . . . . 15V Analog Input Voltage (VS) . . . . . . . . . . . . . . . . . . . . . . . . VSUPPLY Logic Low Level (VAL) . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 0.8V Logic High Level (VAH) . . . . . . . . . . . . . . . . . . . . 4.0V to +VSUPPLY CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. TABLE 1. D.C. ELECTRICAL PERFORMANCE SPECIFICATIONS Device Tested at: +VSUPPLY = +15V, -VSUPPLY = -15V, GND = 0V, Unless Otherwise Specified. D.C. PARAMETERS Switch "ON" Resistance SYMBOL rDS CONDITIONS VA1 = 4.0V, VD = 10V, IS = -10mA, VA2 = 0.8V, S1 /S2/S3/S4 VA1 = 0.8V, VD = -10V, IS = 10mA, VA2 = 4.0V, S1 /S2/S3/S4 Source "OFF" Leakage Current IS(OFF) GROUP A SUBGROUPS 1 2, 3 1 2, 3 1 2, 3 1 2, 3 1 2, 3 1 2, 3 1 2, 3 1 2, 3 1 2, 3 TEMPERATURE (oC) 25 -55 to 125 25 -55 to 125 25 -55 to 125 25 -55 to 125 25 -55 to 125 25 -55 to 125 25 -55 to 125 25 -55 to 125 25 -55 to 125 25 -55 to 125 25 -55 to 125 25 -55 to 125 25 -55 to 125 25 -55 to 125 MIN -1 -100 -1 -100 -1 -100 -1 -100 -1 -100 -1 -100 -1.0 -1.0 -1.0 -1.0 -10 -100 -10 -100 MAX 50 75 50 75 1 100 1 100 1 100 1 100 1 100 1 100 1.0 1.0 1.0 1.0 10 100 0.5 1.0 - UNITS nA nA nA nA nA nA nA nA nA nA nA nA A A A A A A mA mA A A A A VS = +14V, VD = -14V, VA1 = 0.8V, VA2 = 4.0V, S1 /S2/S3/S4 VS = -14V, VD = +14V, VA1 = 4.0V, VA2 = 0.8V, S1 /S2/S3/S4 Drain "OFF" Leakage Current ID(OFF) VS = +14V, VD = -14V, VA1 = 0.8V, VA2 = 4.0V, S1 /S2/S3/S4 VS = -14V, VD = +14V, VA1 = 4.0V, VA2 = 0.8V, S1 /S2/S3/S4 Channel "ON" Leakage Current ID(ON) VD = VS = +14V, VA1 = 4.0V, VA2 = 0.8V, S1 /S2/S3/S4 VD = VS = -14V, VA1 = 0.8V, VA2 = 4.0V, S1 /S2/S3/S4 Low Level Input Current High Level Input Current Supply Current IAL All Channels VAL = 0.8V IAH All Channels VAH = 4.0V 1 2, 3 +ICC All Channels VA = 0.8V 1 2, 3 VA1 = 0V, VA2 = 4.0V and VA1 = 4.0V, VA2 = 0V Supply Current -ICC All Channels VA = 0.8V 1 2, 3 1 2, 3 VA1 = 0V, VA2 = 4.0V and VA1 = 4.0V, VA2 = 0V 1 2, 3 2 HI-303/883 TABLE 2. A.C. ELECTRICAL PERFORMANCE SPECIFICATIONS Device Tested at: +VSUPPLY = +15V, -VSUPPLY = -15V, GND = 0V, Unless Otherwise Specified. GROUP A SUBGROUPS 9 10, 11 9 10, 11 TEMPERATURE (oC) 25 55 to 125 25 55 to 125 PARAMETERS Turn "ON" Time SYMBOL tON CONDITIONS CL = 33pF, RL = 300 CL = 33pF, RL = 300 MIN - MAX 300 500 250 450 UNITS ns ns ns ns Turn "OFF" Time tOFF TABLE 3. ELECTRICAL PERFORMANCE SPECIFICATIONS (NOTE 1) Device Tested at: +VSUPPLY = +15V, -VSUPPLY = -15V, GND = 0V, Unused Pins are Grounded. PARAMETERS Switches Input Capacitance Driver Input Capacitance SYMBOL CIS (OFF) CC1 CC2 Switch Output Capacitance Off Isolation Cross Talk Charge Transfer NOTE: 1. Parameters listed in Table 2 are controlled via design or process parameters and are not directly tested at final production. These parameters are lab characterized upon initial design release, or upon design changes. These parameters are guaranteed by characterization based upon data from multiple production runs which reflect lot to lot and within lot variation. TABLE 4. ELECTRICAL TEST REQUIREMENTS MIL-STD-883 TEST REQUIREMENTS Interim Electrical Parameters (Pre Burn-in) Final Electrical Test Parameters Group A Test Requirements Groups C & D Endpoints NOTE: 2. PDA applies to Subgroup 1 only. SUBGROUPS (Tables 1 and 2) 1 1 (Note 2), 2, 3, 9, 10, 11 1, 2, 3, 9, 10, 11 1 COS VISO VCT VCTE CONDITIONS Measured Source to GND VA = 0V VA = 15V Measured Drain to GND f = 1MHz, VGEN = 1VP-P f = 1MHz, VGEN = 1VP-P VS = GND, CL + 0.01F NOTE 1 1 1 1 1 1 1 TEMPERATURE (oC) 25 25 25 25 25 25 25 MIN 40 40 MAX 28 10 10 28 15 UNITS pF pF pF pF dB dB mV 3 HI-303/883 Test Circuits +VCC S +VCC D ID S VIN IIN D VS VD VIN GND -VCC GND -VCC FIGURE 1. INPUT LEAKAGE CURRENT FIGURE 2. ID (OFF) +VCC VS S IS VD VIN +VCC S D ID(ON) VIN V GND -VCC GND -VCC FIGURE 3. IS (OFF) FIGURE 4. ID (ON) S +VCC D TO MEASUREMENT CIRCUITRY WITH INPUT RESISTANCE OF 1m OR GREATER 0.01MF I1 DRIVER f = 1kHz SQUARE WAVE TR 20ms D VIN (DRIVER) VIN IF PULSE TEST IS USED: TR, TF 20ms S GND I2 VCTE -VCC DROOP CAUSED BY DEVICE LEAKAGE AND MEASUREMENT CIRCUITRY SWITCHING TRANSIENT NOTE: VCTE may be a positive or negative value. FIGURE 5. SUPPLY CURRENTS FIGURE 6. CHARGE TRANSFER ERROR 4 HI-303/883 Test Circuits (Continued) +VCC S D S D VIN VD VGEN = 1VP-P 1k f = 1MHz GND -VCC FIGURE 7. RDS FIGURE 8. OFF CHANNEL ISOLATION S VGEN S D D VGEN = 1VP-P 1k 1k 1k f = 1MHz FIGURE 9. CROSSTALK BETWEEN CHANNELS Test Waveforms 15V +15V V+ S VS = +3V RL LOGIC INPUT GND V-15V D VO CL LOGIC INPUT GND V-15V VS1 = +3V SWITCH OUTPUT VS2 = +3V S1 S2 V+ D1 D2 OUT 2 RL2 CL2 RL1 CL1 OUT 1 FIGURE 10. FIGURE 11. 5 HI-303/883 Test Waveforms (Continued) LOGIC "1" = SWITCH ON LOGIC INPUT 0V VS 90% 0V SWITCH OUTPUT tOFF tON 10% VINH 50% 50% LOGIC INPUT 0V LOGIC "1" = SWITCH ON VINH 50% 0V SWITCH OUTPUTS 50% 0V tOPEN 50% OUT 1 OUT 2 50% tOPEN FIGURE 12. MEASUREMENT POINTS NOTES: 3. RL = RL1 = RL2 = 300; CL = CL1 = CL2 = 33pF FIGURE 13. TTL LOGIC INPUT 4. VINH = 4V RISETIME (0.4V to 3.6V) 20ns FALLTIME (3.6V to 0.4V) 20ns Burn-In Circuit +V 1 NC R1 2 S3 3 D3 4 D1 R2 5 S1 6 A1 7 GND S2 10 A2 9 -V 8 C2 D2 S4 13 D4 12 D2 11 R3 +V 14 R4 C1 D1 -V HI-303/883 CERAMIC DIP NOTES: 5. R1 = R2 = R3 = R4 = 10k, 5%, 1/4 or 1/2W 6. C1 = C2 = 0.01F (per socket) or 0.1F (per row) 7. D1 = D2 = IN4002 (per board) 8. |(V+) - (V-)| = 30V 6 HI-303/883 Schematic Diagram V+ D2A 200 LOGIC IN D1A GND VSWITCH CELL DRIVER (ONE PER SWITCH CELL) MN1A MN2A MN3A MN4A MN5A MN6A MN7A MN8A MP1A MP2A MP3A MP4A MP5A MP6A MP7A MP8A A A FIGURE 14. DIGITAL INPUT BUFFER AND LEVEL SHIFTER A V+ MN1B MN2B MP5B IN MP4B MN3B OUT MN4B MN6B MP3B MP2B MP1B V- A FIGURE 15. SWITCH CELL 7 HI-303/883 Typical Performance Curves 80 DRAIN TO SOURCE ON RESISTANCE () DRAIN TO SOURCE ON RESISTANCE () V+ = +15V, V- = -15V TA = 25oC, V+ = +15V, V- = -15V, Unless Otherwise Specified. 80 TA = 25oC D 60 125oC 25oC -55oC 60 C 40 40 B A 20 20 A B C D V+ = +15V, V- = -15V V+ = +10V, V- = -10V V+ = +7.5V, V- = -7.5V V+ = +5V, V- = -5V -10 -5 0 5 10 15 0 -15 -10 -5 0 5 10 15 0 -15 DRAIN VOLTAGE (V) DRAIN VOLTAGE (V) FIGURE 16. rDS(ON) vs VD AND TEMPERATURE 100 V+ = +15V, V- = -15V TA = 25oC, VS = 15V, RL = 2K POWER DISSIPATION (mW) FIGURE 17. rDS(ON) vs VD AND POWER SUPPLY VOLTAGE 100 V+ = +15V, V- = -15V CLOAD = 3pF, VS = 1VRMS 80 OFF ISOLATION (dB) RL = 100 60 RL = 1k 40 10 HI-300 THRU HI-303 1.0 20 HI-304 THRU HI-307 0.1 1 10 100 1K 10K 100K 1M LOGIC SWITCHING FREQUENCY (50% DUTY CYCLE) (Hz) 0 105 106 107 108 FREQUENCY (Hz) FIGURE 18. DEVICE POWER DISSIPATION vs SWITCHING FREQUENCY (SINGLE LOGIC INPUT) 10.0 V+ = +15V, V- = -15V ID(ON) - CHANNEL LEAKAGE (nA) FIGURE 19. OFF ISOLATION vs FREQUENCY 10.0 V+ = +15V, V- = -15V | VD | = | VS | = 14V SOURCE OR DRAIN OFF LEAKAGE CURRENT (nA) 1.0 1.0 0.1 0.1 0.01 25 75 125 TEMPERATURE (oC) 0.01 25 75 125 TEMPERATURE (oC) FIGURE 20. IS(OFF) OR ID(OFF) vs TEMPERATURE (Note) NOTE: FIGURE 21. ID(ON) vs TEMPERATURE (Note) The net leakage into the source or drain is the N-Channel leakage minus the P-Channel leakage. This difference can be positive, negative or zero depending on the analog voltage and temperature, and will vary greatly from unit to unit. 8 HI-303/883 Typical Performance Curves 60 OUTPUT ON CAPACITANCE (pF) TA = 25oC, V+ = +15V, V- = -15V, Unless Otherwise Specified. (Continued) 16 INPUT CAPACITANCE (pF) 50 12 40 8 TRANSITION (INDETERMINATE DUE TO ACTIVE INPUT) HI-300 THRU HI-303 30 4 TRANSITION HI-304 THRU HI-307 20 0 2 4 6 8 10 12 14 16 DRAIN VOLTAGE (V) 0 2 4 6 8 10 12 14 16 INPUT VOLTAGE (V) FIGURE 22. OUTPUT ON CAPACITANCE vs DRAIN VOLTAGE FIGURE 23. DIGITAL INPUT CAPACITANCE vs INPUT VOLTAGE 300 V+ = +15V, V- = -15V VINH = 4.0V, VINL = 0V SWITCHING TIME (ns) tON 200 SWITCHING TIME (s) V+ = +15V, TA = 25oC VINH = 4V, VINL = 0V 300 tON 200 tOFF tOFF 100 100 -55 -35 -15 5 25 45 65 85 105 125 0 5 10 15 TEMPERATURE (oC) NEGATIVE SUPPLY (V) FIGURE 24. SWITCHING TIME vs TEMPERATURE FIGURE 25. SWITCHING TIME vs NEGATIVE SUPPLY VOLTAGE SWITCHING TIME/BREAK-BEFORE-MAKE TIME (s) 1.8 1.6 1.4 1.2 1.0 0.8 0.6 7 INPUT SWITCHING THRESHOLD (V) V- = -15V, TA = 25oC VINH = 4.0V, VINL = 0V V- = -15V, TA = 25oC 6 5 4 3 2 HI-300 THRU 303 1 0 5 10 15 0 5 10 15 POSITIVE SUPPLY VOLTAGE (V) HI-304 THRU HI-307 tON 0.4 0.2 0 0 tBBM HI-301/303 ONLY tOFF POSITIVE SUPPLY VOLTAGE (V) FIGURE 26. SWITCHING TIME AND BREAK-BEFORE-MAKE TIME vs POSITIVE SUPPLY VOLTAGE FIGURE 27. INPUT SWITCHING THRESHOLD vs POSITIVE SUPPLY VOLTAGE 9 HI-303/883 Die Characteristics DIE DIMENSIONS: 76 mils x 83.9 mils x 19 mils METALLIZATION: Type: Aluminum Thickness: 16kA 2kA GLASSIVATION: Type: Nitride Thickness: 7kA 0.7kA DIE ATTACH: Material: Gold/Silicon Eutectic Alloy Temperature: Ceramic DIP - 460C (Max) WORST CASE CURRENT DENSITY: 3.9 x 105A/cm2 at 30mA This device meets Glassivation Integrity Test requirement per MIL-STD-883 Method 2021 and MIL-M-38510 paragraph 3.5.5.4 Metallization Mask Layout HI-303/883 D2 S2 IN2 D4 12 11 10 9 S4 V+ S3 13 8 14 7 GND 2 V- 3 D3 4 D1 5 S1 6 IN1 10 HI-303/883 Ceramic Dual-In-Line Frit Seal Packages (CERDIP) c1 -A-DBASE METAL E b1 M -Bbbb S BASE PLANE SEATING PLANE S1 b2 b ccc M C A-B S AA C A-B S D Q -CA L DS M (b) SECTION A-A (c) LEAD FINISH F14.3 MIL-STD-1835 GDIP1-T14 (D-1, CONFIGURATION A) 14 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE INCHES SYMBOL A b b1 b2 b3 c MIN 0.014 0.014 0.045 0.023 0.008 0.008 0.220 MAX 0.200 0.026 0.023 0.065 0.045 0.018 0.015 0.785 0.310 MILLIMETERS MIN 0.36 0.36 1.14 0.58 0.20 0.20 5.59 MAX 5.08 0.66 0.58 1.65 1.14 0.46 0.38 19.94 7.87 NOTES 2 3 4 2 3 5 5 6 7 2, 3 8 Rev. 0 4/94 eA c1 D E e eA eA/2 L Q S1 e DS eA/2 c 0.100 BSC 0.300 BSC 0.150 BSC 0.125 0.015 0.005 90o 14 0.200 0.060 105o 0.015 0.030 0.010 0.0015 2.54 BSC 7.62 BSC 3.81 BSC 3.18 0.38 0.13 90o 14 5.08 1.52 105o 0.38 0.76 0.25 0.038 aaa M C A - B S D S NOTES: 9. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer's identification shall not be used as a pin one identification mark. 10. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 11. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 12. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 13. This dimension allows for off-center lid, meniscus, and glass overrun. 14. Dimension Q shall be measured from the seating plane to the base plane. 15. Measure dimension S1 at all four corners. 16. N is the maximum number of terminal positions. 17. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 18. Controlling dimension: INCH. aaa bbb ccc M N All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 11 |
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